About

I have 10+ years of experience in areas as Testing, Hardware, Verification and Sustaining.  Product Life Cycle: from customer requirements with program managers, marketing and systems engineers. Design implementation (schematics capture) with architecture, layout and signal integrity teams. System bring-up, verification and sustaining. 

My skills

Lab tools

Comfortable with lab equipment DMM, DSO/MSO, waveform generator.
Simple SMD soldering.

Communication protocols

Familiar with I2C, USB, SPI, CAN, LIN protocols.

Design

Schematic capture and basic layout: Allegro Design Entry, ORCAD, KiCAD.

Debug

System enabling and debug using Linux environment able to work against aggressive deadlines.

Soft

Team player, familiar with Agile methodology.
Lifelong learning.

I'm an Applications Engineer

On 2018 I started working at Avnet in the Design Creation team.

My career

Second Level Applications Engineer at Avnet

Demand Creation Team:

  • Technical support for customer’s system level based on LoRa technology. 
  • Field Technology Consultant system level solutions for all vertical markets based but not limited to RF/Microwave applications.
  • FAE assistance block diagram generation based on RF front end: LoRa, Bluetooth/BLE, WiFi, GPS, LTE/5G and other Wireless technologies.
  • Cross-reference based on MPN or schematics.

April 2018 to current

JICA Computer trainee at Kanazawa Institute of Technology.

Sub-course: Embedded Systems Computer Architecture Course: 

  • Design of functional digital circuit modules bottom-top and top-bottom approach using logic-gate, truth table, flow diagrams and state-transition charts using Visual Elite suite and creating test benches.
  • Co-development with a Software Engineer of an indoor crops incubator based on Raspberry Pi.
    Power breakout board design (architecture, schematics and PCB).
  • Sensor selection and testing. CO2, pH, Electrical Conductivity, water level, temperature and humidity.
    Module integration, control of actuators: solenoid valve, peristaltic pumps, RGB LEDs and humidifier.

May 2017 to Nov 2017

Hardware Engineer at Continental

Advance Driver Assistance Systems (ADAS):

  • Power distribution board for Short Range Radar (SRR) series production support 3+ variants.
  • Worked with systems and validation engineers gathering design requirements using DOORs.
  • PTN and PCN revisions with program managers and customer defining design component change list.
  • BOM control and Schematics updates based on design change list, design revisions with technical lead.
  • Electromagnetic Compatibility test plan updates for each variant as per customer requirements and industry regulation.

Jun 2016 to Jan 2017

Hardware Engineer at Intel

Data Center Group (DCG):

  • Schematics electrical integration using Cadence Concept Design Entry HDL. Logical and Physical symbols creation using Allegro suite. Closely work with layout, signal integrity, materials and manufacturing teams.
  • Commonality design group: Chipset GPIOs mapping management and HW straps.BOM generation, schematics management and control for Original Design Manufacturer (ODM) reference.
  • Clock schematics PCIe Gen3 clock buffering and peripheral clock generator.
  • Base Management Controller (BMC) schematics: temperature sensors, power sensors, voltage sensor, fans (PWM and tach), I2C/SMBus, SPI and JTAG.

Jul 2012 to Jun 2016

Test Engineer at IBM

Integrated Supply Chain (ISC):

IBM XIV Gen3 high end storage:

  • UNIX based environment test execution and monitoring of interfaces such as iSCSI, SATA/SAS, power ATS and UPS.
  • Diagnose root cause and solution development to keep tests on track.
  • Bash and python code debugging for test execution continuity.
  • Failure analysis and second box 1U drawer level.
  • Process optimization, control, cycle time and yield learning.

Jul 2009 to Jul 2012

My Education

Masters in Electronic Design Instituto Tecnológico de Estudios Superiores de Occidente, Jalisco, Mex 2016

Electronics and Communications Engineering, Universidad del Valle de Mexico, Jalisco, Mex 2009

Others

Japanese-Language Proficiency Test N4            2019

Japanese-Language Proficiency Test N5          2017

Diplôme d’Études en Langue Française B1     2012

I’m ready when you are!